TSMC announced the first 7+ nanometer (nm) chip with partial ultra-violet (EUV) microshadow technology, and will begin risk production with a full EUV process of 5nm next April.
According to TSMC's updated data, its advanced process nodes continue to increase in area and power, but the chip speed cannot be pushed forward at its historical speed.To make up for this, TSMC has updated six encapsulation technologies it developed to speed up interconnections between chips.
In addition, TSMC is also working with four industry partners, including Cadence, to support the online service of back-end chip design.Proponents say cloud-based services will shorten time and expand the range of chip design tools that help extend the semiconductor industry, which is facing a slowdown under Moore's Law.However, they also note that cloud design is still in the early stages of needing to set up and optimize custom platforms.
In terms of technology, TSMC has announced that it will use N7+ process nodes for client chips, which will use EUV that can handle 4 layers of light.Its N5 EUV can be raised to handle up to 14 layers of gloss and will be ready for a risk trial in April.The EUV technology is expected to reduce the number of masks required for advanced designs, thereby reducing costs.
Rival Samsung has also accelerated its adoption of EUV at 7nm node.In addition, Intel doesn't expect to use EUV anytime soon, while Globalfoundries announced in August that it was suspending research and development spending on 7nm and EUV, according to analysts.
TSMC said that the N5 chip will bring 14.7 percent to 17.7 percent speed improvement and reduce its occupied area by 1.8 percent to 1.86 percent, according to tests using the Arm A72 core.N7+ process nodes can reduce power and increase density by 6 ~ 12%.However, TSMC did not say how much the speed of the N7+ could be increased.
Currently, chip designs based on N5 technology nodes are up and running, but most EDA tools won't be available for version 0.9 until at least November.Many of TSMC's base IP modules are already in place for the N5, but some specifications, including PCIe Gen 4 and USB 3.1, may not be in place until June.
The N7+ technology nodes use tighter metal line-spacing and contain a single fin library that helps reduce dynamic power.A car design version will also be available next April.Hou yongqing, deputy general manager of TSMC's research development/design and technology platform, said N7+ provides "" almost the same simulation performance as N7" ".
TSMC said the transistor density of N7 was 16.8 times higher than the 40nm node of the foundry.Unfortunately, the cost of better technology is also rising.According to one of the sources, the total cost of the N5's design, including labor and IP licensing, is about $200 million to $250 million, up sharply from the $150 million currently required for 7nm chips.
Planar technology and packaging technology layout
In addition, TSMC offers two planar 22nm processes.Its goal is to compete with Globalfoundries and samsung's fd-soi process.Globalfoundries announced more than 50 design orders for its 22nm fd-soi late last month.
By the end of this year, engineers are expected to be able to deploy designs using TSMC's 22ULP and ULL processes, which typically follow 28nm design rules and support 0.8 to 0.9V.However, some of the IP available for the 22nm node is not expected to be available until June next year, including PCIe Gen 4, DDR4, LPDDR4, HDMI 2.1 and USB 3.1 blocks.
The 22-nm ULP version dedicated to high performance increased speed by up to 10%, reduced power consumption by 20%, and was 10% lower than the 28-hpc + version.The goal of the ULL version is to provide minimal power consumption for designs such as bluetooth chips.A 1.05 to 0.54V version is expected to be ready and optimized for analog circuits by April.
Aiming at packaging technology, hou yongqing and updated TSMC's wafer fan-out technology, especially the two integrated Fan Out (InFO) technology for interconnected smart phone application processors and memory.
Integrated fan-out package -- InFO-on-Substrate is a chip priority process, with 2 micron interconnection between SoC and 40nm SoC I/O spacing.At present, 65mm2 chip is available for mass production.Info-memory-on-substrate will be put into mass production before the end of the year for linking logic and typical HBM Memory on the full 830mm2 mask.
TSMC's 2.5d process, which USES a C4 convex point spacing of 180 to 150 microns, is expected to reach 130 microns by the end of this year.TSMC will also extend its 1.5-fold mask to use a two-fold mask in April next year to support designs such as large gpus and some network ASIC.
Another type of Integrated chip System (system-on-integrated Chips);SoIC) will obtain EDA's support and OEM certification by may next year.The design path is through a silicon perforation (TUV) to connect convex blocks with spacing less than 10 microns, for linking one or two chips to each other's stacks."" this is another way to improve performance and memory bandwidth," "hou said.