1. Inductance is used in filtering. What is the method of capacitance value?
The selection of inductance value not only considers the noise frequency that wants to filter out, but also considers the reaction capacity of instantaneous current.
If the output end of LC will have the opportunity to output a large current in an instant, the inductance value will be too large to block the speed of the current flowing through the inductor, increasing the ripple noise.
The capacitance value is related to the tolerance of ripple noise specification value.
The smaller the requirement of ripple noise, the larger the capacitance.
The capacitance of ESR/ESL will also have an impact.
In addition, if the LC is placed at the output end of the switching power supply, it is important to note the influence of the pole zero generated by this LC on the stability of the negative feedback control loop.
2. The filtering of analog power source is usually carried out by LC circuit.
But why is LC sometimes worse than RC filtering?
The comparison between LC and RC filtering effect must consider whether the frequency band and inductance value to be filtered are appropriate.
Because the reactance is related to the inductance value and frequency.
If the noise frequency of the power supply is low and the inductance value is not large enough, then the filtering effect may not be as good as RC.
However, the cost of using RC filtering is that the resistance itself consumes energy and is inefficient, and attention should be paid to the power of the selected resistance.
3. Under the condition that the size of the circuit board is fixed, if more functions need to be included in the design, the walking density of the PCB will often be increased, but this may lead to the enhancement of the mutual interference of the walking line. At the same time, too small the running line will not reduce the impedance.
Crosstalk interference is of particular concern when designing high speed and high density PCB, because it has a great influence on timing and signal integrity.
Here are a few points to note:
1). Control the continuity and matching of characteristic impedance of wire running.
2). Size of line spacing.
It is commonly seen that the spacing is twice the line width.
Through simulation, the effect of line spacing on time sequence and signal integrity can be known, and the tolerable minimum spacing can be found out.
The results may vary from chip to chip.
3). Select the appropriate terminal mode.
4). Avoid the same direction of the upper and lower adjacent layers, and even the upper and lower layers overlap together, because the crosstalk is larger than that of the adjacent layers.
5). Blind /buried via is used to increase the routing area.
But the production cost of PCB board will increase.
It's hard to achieve full parallelism and equilength in actual execution, but try to do it anyway.
In addition, differential and common-mode terminals can be reserved to mitigate the impact on the integrity of timing and signal.
4. How to meet EMC requirements as far as possible without causing too much cost pressure?
PCB cost will increase as a result of EMC is usually due to the increased number of strata to strengthen the shielding effect and increase the ferrite bead, choke, suppress the high frequency harmonic components.
In addition, it is usually necessary to match the shielding structure on other mechanisms to make the whole system pass the requirement of EMC.
The following provides only a couple of ways to reduce the electromagnetic radiation effects of the circuit in terms of PCB design techniques.
1), as far as possible choose signal slope (slew rate) slower device, in order to reduce signal generated by the high frequency component.
2) pay attention to the placement of high frequency devices, not too close to external connectors.
3) pay attention to the impedance matching of high-speed signals, and take the line layer and its current path to reduce the reflection and radiation of high frequency.
4) sufficient and appropriate uncoupling capacitors are placed at the power pin of each device to mitigate the noise in the power layer and layer.
Special attention should be paid to whether the frequency response of the capacitor and the characteristic of temperature meet the design requirements.
5) the ground adjacent to the external connector can be properly divided with the ground layer, and the ground adjacent to the connector can be connected to the chassial ground.
6) ground guard/shunt traces can be used properly at some special high speed signals.
Note, however, the effect of guard/shunt traces on the characteristic impedance of walking.
7) the power layer shrinks by 20H compared to the formation, and H is the distance between the power layer and the formation.
5. How to consider impedance matching when designing high speed PCB design schematic diagram?
Impedance matching is one of the elements of high speed PCB circuit design.
The impedance has an absolute relationship with the way of wire running, for example, walking on the surface layer (microstrip) or the inner layer (stripline/double stripline), and the distance from the reference layer (power layer or stratum), the width of wire running, and the PCB material will all influence the characteristic impedance of wire running.
Here, we must say that huaqiang PCB pays special attention to the processing of production data and control of production process of impedance plate, so as to ensure that PCB products can meet the impedance value required by designers.
6. In high-speed PCB design, what aspects should designers consider EMC and EMI rules?
In general EMI/EMC design, both radiated and conducted aspects should be considered. The former belongs to the part with higher frequency (>30MHz) and the latter is the part with lower frequency (<30MHz).
7. Where can I provide a more accurate IBIS model library?
The accuracy of IBIS model directly affects the simulation results.
Basically IBIS can be regarded as the actual chip I/O buffer equivalent circuit of the electric property data, typically by a model transformation and SPICE, and SPICE materials have absolute relationship with chip manufacturing, so the same device different chip manufacturers, its SPICE materials is different, then converted the IBIS model data will follow.
In other words, if the device of manufacturer A is used, only they have the ability to provide accurate model data of their device, because no one else will know better than them what process their device is made of.
If the IBIS provided by a vendor is inaccurate, the fundamental solution is to keep asking for improvements from the vendor.
8. How to choose EDA tools?
Currently, thermal analysis is not a strong point in PCB design software, so it is not recommended to choose. Other functions 1.3.4 can choose PADS or Cadence at a good price.
Beginners of PLD design can adopt the integrated environment provided by PLD chip manufacturer, and can choose single point tool when designing more than one million doors.
I believe that you burn friends have learned so much about PCB design, and also know that PCB needs to go through more than ten production processes from design to finished products. The quality control of each process affects the performance of PCB products.
In particular, multilayer high density PCB board, the production of the details of strict control.
Huaqiang PCB is the preferred supplier of tens of millions of engineers.