There are many ways to solve the EMI problem. Modern EMI inhibition methods include: using EMI inhibition coating, selecting appropriate EMI inhibition parts and EMI simulation design, etc.Based on the most basic PCB board, this paper discusses the function and design technique of PCB layered stack in EMI radiation control.
The capacitance of appropriate capacity is placed near the IC power pin, which can make the jump of IC output voltage faster.However, the problem does not end there.Due to the limited frequency response of capacitors, the capacitors cannot generate the harmonic power needed to drive IC output cleanly on the full frequency band.In addition, the transient voltage formed on the power confluence will form a voltage drop at both ends of the inductance in the decoupling path, and these transient voltages are the main common mode EMI interference sources.How do we solve these problems?
As far as the IC on our circuit board is concerned, the power layer around IC can be regarded as a good high frequency capacitor, which can collect the energy leakage of discrete capacitors providing high frequency energy for clean output.In addition, the excellent power layer has a smaller inductance, so the transient signals generated by the inductance are also small, thus reducing the common mode EMI.
Of course, the connection from the power layer to the IC power pin must be as short as possible, because the rising edge of the digital signal is faster and faster, and it is better to connect directly to the welding pad where the IC power pin is located, which should be discussed separately.
To control the common-mode EMI, the power layer must be a well-designed pairing of the power layer to facilitate decoupling and to have a sufficiently low inductance.One might ask, how good is good?The answer depends on the level of the power source, the material between the layers, and the working frequency (the function of IC rise time).In general, the spacing between power layers is 6mil and the interlayer is FR4 material, so the equivalent capacitance per square inch of power layer is about 75pF.Obviously, the smaller the layer spacing, the larger the capacitance.
There are not many devices with a rise time of 100 to 300ps, but according to the current development speed of IC, devices with an increase time of 100 to 300ps will occupy a high proportion.For circuits with 100-300ps uptime, 3mil interval will not be applicable to most applications.At that time, it was necessary to use layering technology with spacing less than 1mil and replace the FR4 dielectric materials with materials with high dielectric constant.Now, ceramic and additive plastics can meet the design requirements of 100 to 300ps uptime circuits.
Although new materials and methods may be used in the future, common 1 to 3ns uptime circuits, 3 to 6mil layer spacing, and FR4 dielectric materials are often sufficient to handle high-end harmonics and to make transient signals low enough, that is, common mode EMI can be reduced very low.The PCB layered stack design example presented in this paper assumes that the layers are spaced 3 to 6mil.
From the perspective of signal routing, a good layering strategy should be to place all signal routing in one or several layers, which are adjacent to the power supply layer or the ground layer.For power supply, a good stratification strategy should be that the power layer is adjacent to the ground layer and the distance between the ground layer and the ground layer is as small as possible. This is what we call the "stratification" strategy.
What stack strategies help shield and suppress EMI?The following layered stacking scheme assumes that the power supply current flows over a single layer and that single or multiple voltages are distributed across different parts of the same layer.The case of multiple power layers is discussed later.
4 layer board
There are several potential problems in the design of four layers.First, the traditional four-layer plate with a thickness of 62mil is too wide. Even if the signal layer is in the outer layer, the gap between the power supply layer and the ground layer is still too large.
If cost requirements are Paramount, consider the following two alternatives to the traditional four-tier board.Both of these solutions can improve EMI suppression performance, but only for applications where the density of the components on the board is low enough and there is enough area around the components (to place the required copper coating of the power supply).
The first is the preferred scheme. The outer layer of PCB is the formation, and the middle two layers are the signal/power layer.The power supply on the signal layer USES a wide wire, which makes the path impedance of the power supply current low and that of the signal microstrip path low.From the perspective of EMI control, this is the best 4-layer PCB structure available.In the second scheme, the outer layer goes to the power source and the ground, and the middle two layers go to the signal.Compared with the traditional 4-layer plate, the improvement is smaller, and the inter-layer impedance is as bad as the traditional 4-layer plate.
If you want to control the routing impedance, the above stacking plan should be very careful to place the routing under the power supply and the grounding copper island.In addition, the copper-clad islands on the power supply or formation should be interlinked as much as possible to ensure the DC and low frequency connectivity.
6 layer board
If the density of elements on 4 layers is high, it is better to use 6 layers.However, some lamination schemes in the 6-layer board design have not good enough shielding effect on electromagnetic field, and have little effect on reducing transient signal of power bus.Two examples are discussed below.
In the first case, the power supply and ground are placed on the second and fifth layers respectively. Due to the high impedance of the copper clad in the power supply, the control of common mode EMI radiation is very unfavorable.However, from the point of view of signal impedance control, this method is very correct.
In the second case, the power supply and ground were placed on the third and fourth layers respectively. This design solved the problem of the copper clad impedance of the power supply. Due to the poor performance of the electromagnetic shielding in the first and sixth layers, the EMI of the differential mode was increased.If the number of signal lines on the two outer layers is the least and the routing length is very short (less than 1/20 of the maximum harmonic wavelength of the signal), this design can solve the EMI problem of the differential mode.The non-component and non-routing areas on the outer layer are filled with copper and the copper clad areas are grounded (every 1/20 wave length is interval), so the EMI suppression of the differential mode is particularly good.As mentioned above, the copper-spreading area should be connected with the inner multipoint layer.
Generally, the first and sixth layers are distributed as layers, and the third and fourth layers are connected with power supply and ground.Because there are two layers of double microstrip signal line between the power supply layer and the ground layer, the EMI suppression ability is excellent.The drawback of this design is that the routing layer has only two layers.As mentioned above, if the outer layer is short and copper is laid in the non-routing area, the same stacking can be achieved with the traditional 6-layer plate.
The other 6-layer layout is signals, ground, signals, power supply, ground, signals, which can realize the environment needed for advanced signal integrity design.The signal layer is adjacent to the substratum, and the power layer is paired with the substratum.Clearly, the downside is the layer stack imbalance.
This usually causes problems for processing and manufacturing.The solution is to fill all the blank areas of the third layer with copper. If the copper density of the third layer is close to the power supply layer or the ground layer, this plate can be regarded as a structurally balanced circuit board.The copper filling area must be connected to power or ground.The distance between the connected via holes is still 1/20 of the wavelength, not necessarily everywhere, but ideally should be.
10 layer board
Due to the very thin insulation between layers, the impedance between layers of 10 or 12 boards is very low, and excellent signal integrity is fully expected as long as the layering and stacking are not problematic.It is more difficult to process and manufacture 12 layers at 62mil thickness, and there are not many manufacturers capable of processing 12 layers.
Since there is always an insulating layer between the signal layer and the loop layer, it is not optimal to allocate the middle six layers to go the signal line in the 10-layer design.In addition, it is important to keep the signal layer adjacent to the loop layer, that is, the layout of the board is signal, ground, signal, signal, power supply, ground, signal, signal, ground, signal.
This design provides a good path for the signal current and its circuit current.The appropriate wiring strategy is that layer 1 follows the X direction, layer 3 follows the Y direction, layer 4 follows the X direction, and so on.Visually, layers 1 and 3 are a pair of layers, layers 4 and 7 are a pair of layers, and layers 8 and 10 are the last pair of layers.When the routing direction needs to be changed, the signal line on the first layer should be changed from the "through hole" to the third layer.In fact, it may not always be possible, but as a design concept you should try to stick to it.
Similarly, when the signal's routing direction changes, it should be borrowed through holes from the 8th and 10th layers or from the 4th to the 7th layers.This wiring ensures that the coupling between the forward path and the loop of the signal is most tight.For example, if the signal is routed on the first layer and the loop is routed on the second layer and only on the second layer, the signal on the first layer is still in the second layer even if the signal is transferred from the "through hole" to the third layer, thus maintaining low inductance, large capacitance characteristics and good electromagnetic shielding performance.
What if that's not the case?For example, if the signal line on the first layer passes through the hole to the 10th layer, the loop signal has to find the ground plane from the 9th layer. The loop current needs to find the nearest grounding via the hole (such as the grounding pin of the element such as resistance or capacitance).If you happen to have such a hole nearby, you're in luck.If there is no such close through hole available, the inductance will be larger, the capacitance will be reduced, and the EMI will increase.
When the signal line must pass through the hole to leave the current pair of wiring layers to other wiring layers, it should be close to the hole next to the grounding hole, so that the loop signal can smoothly return to the appropriate ground layer.For the stratified combination of the fourth and seventh layers, the signal loop will return from the power layer or the ground layer (i.e., the fifth or sixth layer) because the capacitive coupling between the source layer and the ground layer is good and the signal is easy to transmit.
Design of multiple power layers
If two power supply layers of the same voltage source need to output large current, the circuit board should be distributed into two power supply layers and the ground layer.In this case, an insulation layer is placed between each pair of power supply layers and the ground layer.In this way, we get the two pairs of equal impedance of equal current confluence.If the stack of the power supply layer causes unequal impedance, shunting is uneven, the transient voltage will be much larger, and EMI will increase dramatically.
If there are more than one supply voltage with different values on the circuit board, multiple supply layers are required accordingly, and it is important to keep in mind to create separate pairings and junctions for different power sources.In both cases, the manufacturer's requirements for balancing structure should be kept in mind when determining the location of the matching power supply layer and the grounding layer on the circuit board.
Given that most engineered circuit boards are 62mil thick, traditional printed circuit boards without blind or buried holes, the discussion in this paper on board layering and stacking is limited to this.The proposed layering scheme may not be ideal for PCB with too large thickness difference.In addition, the method of delamination in this paper is not suitable for PCB with blind or buried holes.
In circuit board design, thickness, hole process and layer number of circuit board are not the key to solve the problem. Good stratified stacking is the key to ensure bypass and decoupling of power confluence, minimize transient voltage of power supply layer or ground layer and shield the signal and the electromagnetic field of power supply.Ideally, there should be an insulating layer between the signal routing layer and its return ground, with a matching layer spacing (or more than one pair) as small as possible.According to these basic concepts and principles, the circuit board can always meet the design requirements.Now that the rise of IC has been short and will be shorter, the techniques discussed in this article are essential to solving EMI shielding problems.