For capacitance installation, the first thing to mention is the installation distance.The capacitance with the smallest capacitance has the highest resonant frequency and the smallest decoupling radius, so it is placed closest to the chip.If you're a little bit larger, you can go a little bit further, and you put the biggest one on the outermost layer.However, all capacitors decoupled to the chip are as close to the chip as possible.
The figure below is an example of placement.The capacitance level in this example generally follows a ten-fold relation.
It is also important to note that, when placed, it is best to be evenly distributed around the chip, for each tolerance level.Generally, the arrangement position of power supply and ground pin is taken into account when designing the chip.Therefore, voltage disturbance exists around the chip, and decoupling must be uniform for the whole chip area.If the 680pF capacitors in the figure above are all placed on the upper part of the chip, due to the decoupling radius problem, the voltage disturbance in the lower part of the chip cannot be well decoupled.
When installing capacitors, pull a small lead from the pad and connect it to the power supply plane via the via hole, as well as the ground end.In this way, the current loop flowing through capacitance is: power supply plane - > through hole - > outlet wire - > capacitance - > welding plate - > outlet wire - > through hole - > ground plane. Figure 2 intuitively shows the current reflux path.
The first method draws a long lead from the pad and connects through the hole, which leads to a large parasitic inductance, which must be avoided, which is the worst way to install it.
The second method is to punch holes at the two ends of the pad next to the pad, which is much smaller than the first method.
The third method is to drill holes on the side of the pad to further reduce the loop area, and the parasitic inductance is smaller than the second one, which is a better method.
The fourth method is to punch holes on both sides of the pad. Compared with the third method, each end of the capacitance is connected to the power plane and ground plane through the hole in parallel, which is smaller than the third kind of parasitic inductance.
The last method is to punch holes directly on the pad, and the parasitic inductance is minimal, but the welding may be problematic, and whether to use depends on the processing capacity and method.Third and fourth methods are recommended.
It's important to note that some engineers, in order to save space, sometimes let multiple capacitors use a common through-hole, which should not be done under any circumstances.The best way to optimize the design of capacitance combination is to reduce the amount of capacitance.
The wider the printed line, the smaller the inductance, the wider the lead wire from the pad to the through hole, and if possible, the same width as the pad.This allows you to use 20mil wide lead wires even if the capacitance is 0402.The outlet line and through hole installation are shown above. Note the various sizes in the figure.