DFM should not be limited to chips, PCB needs it more

- Nov 29, 2018-

While there is much debate about the value, definition, variability, and technology of manufacturability design (DFM), all issues are based on chips.Of course, chip DFM is a key requirement when we start thinking about 45 and 32 nm designs.However, the focus on chip DFM ignores the more important technical need: DFM for printed circuit boards.

We all know that even if the silicon chip is 100 percent perfect, the target system may not work properly if any of the components (such as the package, connector, or circuit board) to which the chip communicates is broken.Many packaging, connector, and PCB suppliers may be pushed by system designers to control their manufacturing tolerances.

However, unless all vendors agree to enforce the specification, for example, a connector with a plus or minus 5% tolerance may not be effective for a PCB system with a plus or minus 10% tolerance.To optimize system design, designers need to study the causality of each component.So far, we have no DFM tools to deal with such design issues.

High-speed systems or signal integrity engineers are usually limited to Spice simulations during the pre-layout design phase.In order to ensure the normal operation of the system, it is necessary to simulate the boundary conditions that can cover all machining tolerances.

For example, changes in wire width, dielectric stack height, dielectric constant and loss tangent values within a PCB can all affect impedance and attenuation.However, only engineers at larger companies have the resources to customize their own scripts to perform thousands of simulations before processing the results.Even so, there are no well-defined criteria for which variables to scan.

The most obvious lack is of a boundary model for packaging and connectors.For high speed design, these models can only be accurately defined by frequency dependent S parameters.However, few vendors provide a good s-parameter model, let alone a boundary model over a wide range of frequencies.

In the post-layout verification stage, accurate extraction and simulation of complex PCB are required to calculate detailed corner and bending.However, few tools are available.

It is clear that common PCB design and validation methods are required.So, what do we need?

Let's focus on two areas.For pre-layout design, for example, it is best to have gui-driven input editors for circuit diagrams that allow designers to easily enter changes to each component, simulate and process results, and report on the generation and impact of each variable.

For the post-layout verification, DFM tool needs to be able to automatically adjust the layout to cover the boundary situation, adopt a fast full-wave extractor to extract parasitic parameters, and use I/O transistor boundary model simulation in circuit simulation.

Only when designers consider poor workmanship in both design and validation can they say they have made a manufacturability design.Only when the tool vendor realizes that the chip is only part of a subsystem, such as a PCB, will DFM eventually become truly relevant to the customer developing the end product.