Advanced circuit assembly technology in the 21st century

- Jul 27, 2018-

Is what people remember the 1990 s, wireless communication flourish, the emergence of multimedia and the development of Internet, the global scope of a sharp increase in information requirement information of data exchange and lose to realize large capacity, high speed and digital, so as to promote the electronic equipment to the rapid development of high performance, high integration and high reliability direction, make the electronic information industry developed rapidly and by leaps and bounds.

To support this development process and key technologies is the development and application of advanced circuit assembly technology.

Advanced circuit assembly technology is a circuit assembly technology composed of advanced IC packaging and advanced SMT.


The recent development of advanced IC packaging technology and the prospect of the 21st century


Electronic components are the cells of electronic information equipment, and plate-level circuit assembly technology is the basis of manufacturing electronic equipment.

The emergence of different types of electronic components will always lead to a revolution in board - level circuit assembly technology.

With the booming development of LSI in the second half of the 1970s, it was replaced by the first generation SMT in the 1980s. The peripheral terminal type packaging represented by QFP has become the mainstream packaging nowadays.

In the 1990s, with the narrow spacing of QFP, the board level circuit assembly technology was faced with challenges. Although the narrow spacing assembly technology (FPT) was developed, many processes of board level circuit assembly with spacing less than 0.4mm were still solved.

As the most ideal solution to the first half of the 90 s the United States the second representative assembly technique of IC side array type packaging (BGA), its further small package is the chip size package (CSP) is in the 90 s of the 20th century has not become the focus of attention, for example, more than 400 needle assembly of practical difficulties of QFP sealing by easy assembling terminals spacing is 1.0-1.5 mm of PBGA and TBGA instead, implements the group of this kind of device to flow again.

In particular, flip chip technology is being used to connect chips to the packaging substrate, enabling thousands of pins of PCBA to be used in supercomputers and workstations, called FCBGA, to begin practical applications.

Third representative assembly technology level chip board assembly directly, but due to the reliability, cost, and KGD is restricted, only in special field application, the further development of IC packaging, at the end of 99 budding chip encapsulation (WLP) planar array bump FC corresponding semiconductor devices to 2014 expected to be more needle and high-performance requirements of the third representative assembly packaging.


IC packaging has been lagging behind the inherent capabilities of IC chips.

We hope that the performance gap between bare chips and packaged chips will be reduced, which will promote the development of new design and packaging technology.

In the new packaging design, the multi-chip packaging (CSP) consists of more than one chip stacked on top of each other, and the interconnection between chips can be realized through wire welding and flip chip design (on-line welding, on-line welding, or on-line welding), which further reduces the weight and space of devices).


Due to the size and cost advantages, Wafer level CSP (Wafer - levelcap) will be further development, the technology is in the chip (chip) before cutting into small squares, it on a chip to form the first level interconnection and packaging I/O terminals, which not only shortened the manufacturing cycle, the I/O terminals can be divided into planar array and the surrounding (according to the distribution of I/O terminals) two types;

For the former, the terminal spacing of EIAJ is less than 0.8mm, and the ultra-small package with the external size of 4mm-21mm is the standard, which is mainly applicable to logic and storage components. For the latter, the non-lead miniaturized sealing bag with peripheral terminals, such as SON and QFN, is mainly applicable to storage devices and low-grade logic devices.

Since the advent of CSP in the early 90 s, this paper puts forward all kinds of structure forms, now with planar array FBGA is the mainstream, the first generation of FBGA type is type of plastics and face down, the second generation FBGA were loaded with face down, all use lead frame plastic module, encapsulation, and a new generation of FBGA is crystal as a carrier for transmission, cutting (line) of the final assembly process, namely the WLP, replace the old encapsulates the connection technology (wire welding, TAB, and flip chip welding), but in front of the line segment, the semiconductor process before wiring technology,

The chip liner is connected to the external terminal, and the subsequent solder ball connection and electrical test are completed in the chip state.

It is obvious that the FBGA of actual chip size is made by WLP, and there is no difference with FC in appearance.


In conclusion, PBGA, TBGA, FBGA, (CSP) and FC are the development trend of IC packaging nowadays.

Table 1 and table 2 respectively show the development trend of these packages.

In the first 15 years of the 21st century, the third representative assembly and packaging will develop rapidly. Around high-density assembly, the diversity of packaging structure will be the most prominent feature of IC packaging at the beginning of the 21st century.

LSI chip laminated packaging, ring packaging: also, there will be new 3D packaging, optoelectronics interconnection, and optical surface assembly technology will flourish.

System level packaging (MCM/SIP) of system level chips (SOC) and MCM will be further developed and put into use with the improvement of design tools, the improvement of wiring density, the adoption of new substrate materials and the popularization of economic KGD supply.


Passive encapsulation


As the industrial and consumer electronics market for electronic device miniaturization, high performance, high reliability, safety and electromagnetic compatibility requirements, continuously put forward new requirements on electronic circuit performance, since the 1990 s, smelting type components to further miniaturization, multiple stratification, large capacity, high voltage and high performance direction development, at the same time, along with the popularization and application of SMT in all electronic equipment, electronic component of use is growing rapidly worldwide, consume electronic component to reach $1 million now, only the ratio of passive components to IC generally greater than 20. Due to the discrete component need so much,

So discrete components dominate the final PCB component size;

In addition, the rapid increase in the amount of chip passive components makes it more difficult to solve the bottleneck in the packaging process through the packaging of chip components, which leads to the imbalance of the production line, the decrease of equipment utilization rate and the increase of cost. Meanwhile, the supply time of chip components takes up 30% of the production line, which seriously affects the increase of production volume.

The effective way to solve these problems is.

Integration of passive components.


Integrated passive components come in the following packaging forms:


Array: many passive components of one type are integrated and encapsulated as face array terminals.


Network: many hybrid resistors and capacitors are integrated and packaged as peripheral terminals.


Hybrid: some passive components and active components are combined for packaging;


Embedding: embedding passive components into PCB or other substrate;


Integration mix: the integrated passive components are packaged in QFP or TSOP formats.


The promotion and application of these passive packaging can effectively solve pasting: bottleneck, improve SMT production line balance, reduce cost, increase production and increase assembly density.