24 tips for reducing noise and electromagnetic interference

- Sep 22, 2018-

As electronic equipment becomes more and more sensitive, which requires more and more anti-interference capability of equipment, PCB design becomes more difficult. How to improve the anti-interference capability of PCB has become one of the key issues that many engineers pay attention to.This paper introduces some tips for reducing noise and electromagnetic interference in PCB design.

Here are 24 tips for reducing noise and electromagnetic interference in PCB design that have been summarized over the years:

(1) use low-speed chips instead of high-speed ones. High-speed chips are used in key places.

(2) the control circuit can be reduced by using a series of resistance.

(3) provide some form of damping for relays, etc.

(4) use the minimum frequency clock that meets the system requirements.

(5) the clock generator is as close as possible to the device using the clock.Quartz crystal oscillator case to be grounded.

(6) use the land line to circle the clock zone, and the clock line should be as short as possible.

(7) I/O drive circuit should be as close to the edge of the printing plate as possible to get it out of the printing plate as soon as possible.The signals coming into the PCB should be filtered and the signals coming from the high noise area should be filtered as well. At the same time, the signal reflection should be reduced by the series terminal resistance method.

(8) the MCD useless terminal shall be connected to high, or grounded, or defined as the output terminal, and the terminal of the integrated circuit shall be connected to the power source ground, not suspended.

(9) the idle gate input terminal should not be suspended, the idle operation put positive input terminal is grounded, and negative input terminal is connected with output terminal.

(10) as far as possible, the printing plate USES 45 broken lines instead of 90 broken lines to reduce the emission and coupling of high frequency signals.

(11) the PCB is divided according to the frequency and current switching characteristics, and the noise and non-noise components should be further away from each other.

(12) single panel and double panel shall use single point power supply and single point grounding, power cord and ground wire to be as thick as possible. It is economical to use multi-layer board to reduce power supply and ground capacitive inductance.

(13) keep clock, bus, and chip selection signals away from I/O lines and connectors.

(14) the analog voltage input line and reference voltage end should be as far away from the digital circuit signal line as possible, especially the clock.

(15) for A/D devices, the digital part and the analog part should be unified rather than intersect.

(16) the clock line perpendicular to the I/O line has less interference than the parallel I/O line, and the clock element pin is far away from the I/O cable.

(17) the component pin is as short as possible, and the decoupling capacitance pin is as short as possible.

(18) the key lines should be as thick as possible and add a protective cover on both sides.High-speed lines should be short and straight.

(19) the line sensitive to noise should not be parallel to the high-current, high-speed switching line.

(20) do not run under the quartz crystal and under the noise sensitive device.

(21) weak signal circuit, do not form a current loop around the low-frequency circuit.

(22) neither signal should form a loop. If it is unavoidable, make the loop area as small as possible.

(23) one decoupling capacitance per integrated circuit.A small high frequency by-pass capacitance is added to each electrolytic capacitor.

(24) use tantalum capacitors with large capacity or polycoolant capacitors instead of electrolytic capacitors as charging and discharging energy storage capacitors.When using tubular capacitors, the casing should be grounded.